Generally, while a thin film transistor (TFT) is widely used as a switching element for switching the pixel data and formed in the respective pixel area of liquid crystal display (LCD), it also can be used as a load resistor in a static random access memory (SRAM) with memory capacities of 1 Mb.
The circuit diagram of FIG. 1 is the memory cell of a SRAM which employs a p channel TFT as a load element instead of the load resistor.
A memory cell unit or basic storage cell consists of a single flip-flop having cross-coupled inverters, whereby each of the inverters includes n channel MOS transistors Q1, Q2 and p channel TFT Q5, Q6 used as a load.
The data lines B/L, *B/L (here * means the bar) are connected to the source and drain of n channel MOS transistors Q3, Q4 in memory cell unit whose gate is connected to the word line W/L.
The data of logic "1" can be written to the selected cell by applying high and low level signals into the bit lines B/L and *B/L, respectively. This state causes transistor Q1 to turn off and transistor Q2 to turn on, thereby charging up the node point N1 through a transistor Q3 and continuing to retain the stored data.
Conversely, the data of logic "0" can be written to the selected cell by applying low and high level signals into the bit lines B/L and *B/L, respectively. Such a state causes transistor Q1 to turn on and transistor Q2 to turn off, thereby charging up node point N2 through a transistor Q4 and continuing to retain the stored data.
The standby current Isb can be expressed as the sum of the off current Ioff of PMOS transistor Q6 and the leakage current Ileak of NMOS transistor Q1 as follows: EQU Isb=Ioff+Ileak (1)
The leakage current Ileak of NMOS transistor Q1, which is generally about 10 fA, must be smaller than the on current Ion of PMOS transistor Q5 (that is, Ion&gt;Ileak.times.100).
Accordingly, in SRAMs with capacities of 4 Mb having the standby current Isb above 1 .mu.A, the current value of 250 fA per the unit cell can be obtained and then it is known that Ileak.apprxeq.10 fA/cell, Ioff.ltoreq.250 fA/cell from the above Eq.(1).
To make high quality SRAM having reduced power consumptions and improved data retention features means, the off current of the PMOS transistor must be reduced and the on current increased.
The recent research being based upon such a principle is developed with the aim of improving the ratio of on to off current.
With reference to the accompanying drawings, the conventional method for fabricating p type TFT with an object of an improvement of the on/off current ratio is simply described.
FIGS. 2a and 2D are sectional views showing the conventional process for fabricating a p type TFT and FIG. 3 illustrates the lattice structure associated with the body polycrystalline silicon layer of the p type TFT. The main features in fabricating the conventional p type MOS transistor reside in the formation of the larger grain size of body polycrystalline silicon layer being based upon the bottom gate through the solid phase growth process.
The solid phase growth process is carried out through a long time annealing for about 24 hours in the vicinity of 600.degree. C.
Referring to FIG. 2A, a polycrystalline silicon layer deposited onto an insulated substrate 1 or insulating layer is patterned to form a gate electrode 2 by the conventional photolithography process using the mask having a featured gate electrode pattern therein.
And as shown in FIG. 2B, on the entire surface of the substrate are successively provided a gate insulation layer 3 and a body polycrystalline silicon layer 4 by chemical vapor deposition (CVD) method.
As the solid phase growth process, the annealing step at about 600.degree. C. for 24 hours is performed to obtain the large grain size of the body polycrystalline silicon layer 4.
The channel area is masked by the patterned photoresist layer through the exposure and development of the coated resist layer on the body polycrystalline silicon layer 4.
The masking area covering the channel area is defined so as to produce the overlapped portion between the source area 6a to be formed and the gate electrode 2, and to secure the off-set between the drain area 6b and the gate electrode 2 to be formed. In the drawing, a, b, c and d denote a source area, a channel area, an off-set area and a drain area, respectively.
The source and drain areas 6a and 6b are formed by the ion implantation of p-type impurity such as BF2 into the revealed body polycrystalline silicon layer 4, ultimately to form a p type TFT.
So as to obtain an improved p type TFT, the grain size has been increased by the solid phase growth process, but the channel area as indicated as b in FIG. 3 has the grain boundary that reduces the on current of the TFT. Further the grain boundary is also across both ends of the respective junctions of the source and drain, thereby increasing the off current.